1. Technical Field
Embodiments of the present invention relate to features of a Field Programmable Gate Array (FPGA) programmed to form a system including a First In First Out (FIFO) communication buffer. More particularly, the present invention relates to efficient implementation of FIFO communication buffers to distribute data from a single source to multiple data sink devices.
2. Related Art
Conventional processor based systems use some form of memory controller in order to access memory devices and provide arbitration for devices connected to the memory controller ports, such as processors or other peripherals. To address the need to configure a memory controller to provide maximum bandwidth when used with various processor systems, a programmable logic device such as a Field Programmable Gate Array (FPGA) has been used to create the memory controller. FPGAs can be used to provide a wide variety of these memory controllers, including single port and multiport memory controllers.
Traditional PLDs such as Field Programmable Gate Arrays (FPGAs) and Complex PLDs (CPLDs) are programmable to form modules that are networked together to communicate. The modules may be complex core devices such as soft processors constructed using FPGA logic, or other less complex components. With the modules potentially operating at different speeds, operating within different clock domains, or otherwise requiring data to be buffered between the modules for communication, a First in First out (FIFO) communication buffer is typically used to interconnect the cores. The FIFOs are often implemented with internal memory, or a combination of registers or other components of the FPGA.
FIG. 1 illustrates the interconnection of modules 2 and 4 using a FIFO 6. The FIFO 6 shown is unidirectional, with a data input (DATAIN) connected to a source module 2 and a data output (DATAOUT) connected to a sink module 4. The signal VALIDIN is asserted when input data from the source 2 is ready for transmission. Similarly, VALIDOUT is asserted from the FIFO 6 when data is stored in the FIFO for transmission. The signal STALLIN is asserted from the FIFO 6 when the FIFO becomes full and cannot accept additional data. Similarly, STALLOUT is asserted from the sink 4 when it is unable to accept data from the FIFO.
FIG. 2 illustrates more details of the FIFO 6 comprising FIFO memory 8 and its FIFO control logic 10. The FIFO memory 8 includes a data input (DA) for receiving the data input signal (DATAIN) and a data output (DB) for receiving the data output signal (DATAOUT). The input data is stored in the FIFO memory 8 at an address (ADDRA) provided from the FIFO control logic 10. Similarly, data read from the FIFO memory 8 is provided using an address (ADDRB) provided from the FIFO control logic 10. The FIFO memory 8 is clocked by a common clock signal CLK received at clock inputs (CLKA & CLKB). The B side output is enabled by a high applied to the enable input (ENB). With the FIFO memory 8 being unidirectional, writing at the output port is disabled by a low applied to the A side write enable input (WEB), while writing at the input port is enabled by a high applied to the B side write enable input (WEA).
The FIFO control logic 10 operates to address data for pushing and popping, and to send valid and stall signals. The FIFO control logic 10 generates the address signals (ADDRA) and (ADDRB) to control pushing or writing of data into memory locations of the FIFO memory 8, as well as to control popping or reading of data. The FIFO control logic 10 ensures that the output valid signal (VALIDOUT) is asserted if there is data in the FIFO memory 8. It further asserts a stall signal (STALLIN) if the FIFO memory 8 becomes full. If a stall signal is received from a sink module, the FIFO control logic 10 does not address a signal for reading at the output address (ADDRB). Similarly, if a valid signal (VALIDIN) is received from a source indicating data is being transmitted, a proper input address (ADDRA) is asserted.
For reference, a block diagram of components of a conventional FPGA that may be used to form source and sink modules and FIFOs that interconnect these modules is provided in FIG. 3. The FPGA includes input/output (IOBs) blocks 32 (each labeled 10) located around the perimeter of the FPGA, multi-gigabit transceivers (MGT) 34 interspersed with the I/O blocks 32, configurable logic blocks 36 (each labeled CLB) arranged in an array, block random access memory 38 (each labeled BRAM) interspersed with the CLBs, configuration logic 33, a configuration interface 31, an on-chip processor 16, and an internal configuration access port (ICAP) 35. The FPGA also includes a programmable interconnect structure (not shown) made up of traces that are programmably connectable between the CLBs 36 and IOBs 32 and BRAMs 38.
The configuration memory array 37 typically includes millions of the SRAM memory cells lying beneath the structure shown in FIG. 3. The configuration memory cells are programmed to configure the CLBs 36, IOBs 32, BRAMs 38 and appropriately connect the interconnect lines. Source and sink modules can be formed from these elements, as well as FIFOs. The BRAM memory 38, in particular, can be used to form a FIFO memory such as device 8 in FIG. 2, while simpler FIFO memories can be formed from registers or logic in the CLBs. The configuration memory array 37 programmed for the configuration can be visualized as a rectangular array of bits. The bits are grouped into frames that are one-bit wide words that extend in columns from the top of the array to the bottom. The configuration data values are typically loaded into the configuration memory array one frame at a time from the external store via the configuration interface 31.
In general, the FPGA of FIG. 3 is configured in response to a set of configuration data values that are loaded into a configuration memory array of the FPGA from an external store via configuration interface 31. The configuration logic 33 provides circuitry for programming of the configuration memory array cells 31 typically at startup. The FPGA can be reconfigured by rewriting data in the configuration memory array 31. In one reconfiguration method, the ICAP 35 is used to rewrite data in the configuration memory array in order to generate or instantiate the FPGAs internal logic (e.g., CLBs 36 and BRAMs 38). Without using the ICAP 35, reconfiguration can also be performed by loading reconfiguration frames through the configuration interface 31 using external customized logic components to over-write frame data in the configuration memory array.
It would be desirable to use the structure of an FPGA to provide an improved FIFO communication buffer for interconnecting modules. In particular, it would be desirable to provide a FIFO communication buffer and operation method that provides low-latency high-throughput data transfer to multiple sink modules while minimizing the amount of memory required for the FIFO memory.